1. Field of the Invention
The present invention is related to the field of integrated circuits. More particularly, the present invention is two related methods and apparatus for determining a binary constant to be output from embedded memory arrays into system logic of an integrated circuit, that maximizes improvement to fault coverage of the system logic.
2. Art Background
In the co-pending U.S. patent application, Ser. No. 07/717,890, filed Jun. 19, 1991, invented by the inventor of the present invention, Marc E. Levitt, assigned to the assignee of the present Application, Sun Microsystems Inc., entitled Method and Apparatus for Improving Fault Coverage of System Logic of an Integrated Circuit with Embedded Memory Arrays, a method and apparatus for improving fault coverage of system logic of an integrated circuit with embedded memory arrays by indirectly enhancing the controllability and observability of the system logic through enhancement to the controllability of the embedded memory arrays is disclosed. The method and apparatus disclosed in the co-pending application has particular application to digital system testing and integrated circuit design.
Fault coverage is the ratio between the number of faults detectable and the total number of faults in the assumed fault universe. Controllability is the ability to establish a specific signal at each node in a circuit by setting values on the circuit's input. Observability is the ability to determine the signal value at any node in a circuit by controlling the circuit's input and observing its outputs. For further description on controllability and observability, see M. Abramovici, M. Breuer, and A. Friedman, Digital System Testing and Testable Design, Computer Science Press, 1990, pp. 345-346.
The method and apparatus disclosed differ from the prior art in that the controllability of the embedded memory arrays is enhanced. As a result, the controllability and observability of the system logic is in turn enhanced, thereby improving the fault coverage of system logic of an integrated circuit with embedded memory. The method and apparatus of the co-pending application modify the embedded memory arrays 14 such that their outputs into the system logic 12 are unaltered during a normal mode of operation (TE=0), and altered to a predetermined binary constant (C) during a test mode of operation (TE=1) when the system logic 12 is being tested, whereby causing controllability of the embedded memory arrays 14 to be enhanced (FIG. 1).
Due to the variety of integrated circuits with embedded memory arrays, various approaches to modifying the embedded memory arrays are disclosed in the co-pending Application. The embedded memory arrays 14 may be modified using multiplexor-based, gate-based or transistor-based binary constant generation/selection circuit 16 (FIG. 1). Alternatively, output latches or sense amplifiers of the embedded memory arrays may be modified to output the predetermined binary constant (C) during the test mode of operation (TE=1).
One intuitively obvious approach to determining the binary constant to be output during the test mode of operation is to generate the binary constant randomly. However, a randomly generated binary constant may not be the most effective binary constant to be used. In fact, empirical evidence has shown that a predetermined binary constant customized for a particular integrated circuit further improves the effectiveness of the method and apparatus for improving fault coverage of system logic of an integrated circuit with embedded memory arrays disclosed in the co-pending Application.
At the other end of the spectrum, another intuitively obvious approach to determining the binary constant to be output during the test mode of operation is performing fault simulation for all possible binary constants and selecting the binary constant with the highest fault coverage. The fault simulation may be performed using a collection of test vectors generated by an automated test generation apparatus under the assumption that output from the embedded memory arrays is uncontrollable.
Fault simulation is the process of stimulating a circuit in the presence of a fault. Test patterns generation is the process of determining the stimuli necessary to cause certain faults in a circuit to be observed. For further description of fault simulation and test generation, see M. Abramovici, M. Breuer, and A. Friedman, Digital System Testing and Testable Design, Computer Science Press, 1990, pp. 131-342.
While the fault simulation and test patterns generation approach will yield the most effective binary constant to be used, it is computationally expensive if there are more than a handful of possible binary constants. 2.sup.n fault simulation runs of m test vectors will be required, if there are m test vectors generated and n bits are output from the embedded memory arrays into the system logic. That is, for 100 test vectors and 5 bits of output from an embedded memory arrays into the system logic, 32 (2.sup.5) fault simulation runs of 100 test vectors are required.
As will be described, the present invention complements the method and apparatus of the co-pending Application, and provides two related methods and apparatus for determining a binary constant to be output from an embedded memory arrays into system logics of an integrated circuit, that maximizes improvement to fault coverage of system logic. The two related methods and apparatus improve the effectiveness of the method and apparatus of the co-pending Application over the random assignment approach, and without requiring the expensive computations of the exhaustive fault simulation of generated test patterns approach.